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s3c7524/c7528/p7528/c7534/c7538/p7538 p roduct overview 1- 1 1 product overview the s3c7524/c7528/c7534/c7538 single-chip cmos microcontroller has been designed for high-performance using sam 47 (samsung arrangeable microcontrollers). sam 47, samsung's newest 4-bit cpu core is notable for its low energy consumption and low operating voltage. you can select from two rom sizes: 4k or 8k bytes except for the difference in rom size, the features and functions of the s3c7524 and the s3c7528, the s3c7534 and the S3C7538 are identical. with it's dtmf generator, watchdog timer function, and versatile 8-bit timer/counters, thes3c7524/c7528 /c5304/c5308 offers an excellent design solution for a wide variety of telecommunication applications. up to 35 pins of the available 42-pin sdip or 44-pin qfp package for the s3c7524/c7528, and up to 23 pins of the available 30-pin sdip or 32-pin sop package for the s3c7534/c7538 can be assign to i/o. six vectored interrupts for s3c7524/c7528 and four vectored interrupts for s3c7534/c7538 provide fast response to internal and external events. in addition, the s3c7524/c7528/c7534/c7538 's advanced cmos technology provides for low power consumption and a wide operating voltage range. otp the s3c7524/c7528 microcontroller is also available in otp (one time programmable) version, s3p7528. the s3c7534/c7538 microcontroller is also available in otp (one time programmable) version, s3p7538. the s3p7528/p7538 microcontroller has an on-chip 8k-byte one-time-programable eprom instead of masked rom. the s3p7528 is comparable to s3c7524/c7528, both in function and in pin configuration. also, the s3p7538 is comparable to the s3c7534/c7538, both in function and in pin configuration.
product overview s3 c7524/c7528/p7528/c7534/c7538/p7538 1- 2 features summary memory 768 4-bit ram 4,096 8-bit rom (s3c7524/c7534) 8,192 8-bit rom (s3c7528/c7538) 35 i/o pins input only: 4 pins (s3c7524/c7528) 1 pins (s3c7534/c7538) i/o: 23 pins (s3c7524/c7528) 14 pins ( s3c7534/c7538) n-channel open-drain i/o: 8 pins memory-mapped i/o structure data memory bank 15 dtmf generator 16 dual-tone frequencies for tone dialing 8-bit basic timer programmable interval timer watchdog timer two 8-bit timer/counters programmable 8-bit timer external event counter function arbitrary clock frequency output watch timer real-time and interval time measurement four frequency outputs to the buz pin bit sequential carrier supports 8-bit serial data transfer in arbitrary format interrupts 3 external interrupt vectors (s3c7524/c7528) 1 external interrupt vectors (s3c7534/c7538) 3 internal interrupt vectors 2 quasi-interrupts power-down modes idle: only cpu clock stops stop: system clock stops oscillation sources crystal, or ceramic for main system clock main system clock frequency: 0.4?6.0 mhz (typical) cpu clock divider circuit (by 4, 8, or 64) instruction execution times 0.95, 1.91, and 15.3 m s at 4.19 mhz 1.12, 2.23, 17.88 m s at 3.58 mhz 0.67, 1.33, 10.7 m s at 6.0 mhz operating temperature ? 40 c to 85 c operating voltage range 2.0 v to 5.5 v package types 42 sdip, 44 qfp (s3c7524/c7528) 30 sdip, 32 sop (s3c7534/c7538)
s3c7524/c7528/p7528/c7534/c7538/p7538 p roduct overview 1 - 3 block diagram p6.0?p6.3 / ks0?ks3 arithmetic and logic unit interrupt control block stack pointer program counter program status word flags instruction decoder clock reset xin xout internal interrupts p8.0?p8.3 p5.0?p5.3 p4.0 / btco p4.1 - p4.3 p7.0?p7.3 / ks4?ks7 p9.0?p9.2 dtmf int0, int1, int2, int4 8-bit timer/ counter 0 8-bit timer/ counter 1 i/o port 6 i/o port 7 p2.0 / tclo0 p2.1 / tclo1 p2.2 / clo p2.3 / buz p3.0 / tcl0 p3.1 / tcl1 p3.2 p3.3 i/o port 4 i/o port 5 dtmf generator p1.0 / int0 p1.1 / int1 p1.2 / int2 p1.3 / int4 input port 1 768 x 4-bit data memory program memory s3c7524/c7534: 4 kbytes s3c7528/c7538: 8 kbytes i/o port 9 i/o port 8 i/o port 2 i/o port 3 basic timer watch timer watch-dog timer note: s3c7534/c7538 does not use p1.1/int1, p1.2/int2, p1.3/int3, p3.2, p3.3, int1, int2, int4, p8.0-p8.3, and p9.0-p9.2. figure 1?1. s3c7524/c7528 simplified block diagram
product overview s3 c7524/c7528/p7528/c7534/c7538/p7538 1- 4 pin assignments p1.0 / int0 p1.1 / int1 p1.2 / int2 p1.3 / int4 p2.0 / tclo0 p2.1 / tclo1 p2.2 / clo p2.3 / buz p3.0 / tcl0 p3.1 / tcl1 v dd v ss x out x in test p4.0 / btco p4.1 reset p3.2 p3.3 p4.2 p9.2 p9.1 p9.0 dtmf p7.3 / ks7 p7.2 / ks6 p7.1 / ks5 p7.0 / ks4 p6.3 / ks3 p6.2 / ks2 p6.1 / ks1 p6.0 / ks0 p5.3 p5.2 p5.1 p5.0 p8.3 p8.2 p8.1 p8.0 p4.3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 s3c7524/c7528 (42-sdip-600) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 1?2. s3c7524/c7528 pin assignment diagrams (42?sdip)
s3c7524/c7528/p7528/c7534/c7538/p7538 p roduct overview 1 - 5 reset p3.2 p3.3 p4.2 nc p4.3 p8.0 p8.1 p8.2 p8.3 p5.0 1 2 3 4 5 6 7 8 9 10 11 p7.3 / ks7 p7.2 / ks6 p7.1 / ks5 p7.0 / ks4 p6.3 / ks3 p6.2 / ks2 p6.1 / ks1 p6.0 / ks0 p5.3 p5.2 p5.1 p2.2 / clo p2.3 / buz p3.0 / tcl0 p3.1 / tcl1 v dd v ss x out x in test p4.0 / btco p4.1 ks57c5204/c5208 (44-qfp-1010b) 12 1 3 1 4 1 5 1 6 1 7 1 8 1 9 20 21 22 33 32 31 30 29 28 27 26 25 24 23 4 4 43 42 41 40 3 9 38 37 36 35 34 p2.1 / tclo1 p2.0 / tclo0 p1.3 / int4 p1.2 / int2 p1.1 / int1 p1.0 / int0 nc p9.2 p9.1 p9.0 dtmf figure 1?3. s3c7524/c7528 pin assignment diagrams (44?qfp)
product overview s3 c7524/c7528/p7528/c7534/c7538/p7538 1- 6 v ss x out x in test p4.0 / btco p4.1 reset p4.2 p4.3 p5.0 p5.1 p5.2 p5.3 p6.0 / ks0 p6.1 / ks1 v dd p3.1 / tcl1 p3.0 / tcl0 p2.3 / buz p2.2 / clo p2.1 / tclo1 p2.0 / tclo0 p1.0 / int0 dtmf p7.3 / ks7 p7.2 / ks6 p7.1 / ks5 p7.0 / ks4 p6.3 / ks3 p6.2 / ks2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 (30-sdip-400) s3c7534/c7538 figure 1?4. s3c7534/c7538 pin assignment diagrams (30?sdip) v ss x out x in test p4.0 / btco p4.1 reset p4.2 nc p4.3 p5.0 p5.1 p5.2 p5.3 p6.0 / ks0 p6.1 / ks1 v dd p3.1 / tcl1 p3.0 / tcl0 p2.3 / buz p2.2 / clo p2.1 / tclo1 p2.0 / tclo0 p1.0 / int0 nc dtmf p7.3 / ks7 p7.2 / ks6 p7.1 / ks5 p7.0 / ks4 p6.3 / ks3 p6.2 / ks2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (32-sop-405a) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 s3c7534/c7538 figure 1?5. s3c7534/c7538 pin assignment diagrams (32?sop)
s3c7524/c7528/p7528/c7534/c7538/p7538 p roduct overview 1 - 7 pin descriptions table 1-1. s3c7524/c7528 pin descriptions pin name pin type reset value description pin number share pin circuit type p1.0 p1.1 p1.2 p1.3 i i 4-bit input port. 1-bit and 4-bit read and test is possible. each pull-up resistors are assignable by software. 1 (39) 2 (40) 3 (41) 4 (42) int0 int1 int2 int4 a-4 p2.0 p2.1 p2.2 p2.3 i/o i 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. 5 (43) 6 (44) 7 (1) 8 (2) tclo0 tclo1 clo buz d-2 p3.0 p3.1 p3.2 p3.3 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. ports 2 and 3 can be paired to enable 8-bit data transfer. 9 (3) 10 (4) 19 (13) 20 (14) tcl0 tcl1 d-4 p4.0 p4.1 p4.2 p4.3 p5.0?p5.3 i/o i 4-bit i/o ports. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. n-channel open-drain or push-pull output can be selected by software (1-bit unit) ports 4 and 5 can be paired to support 8-bit data transfer. 16 (10) 17 (11) 21 (15) 22 (17) 27?30 (22?25) btco e-2 p6.0?p6.3 p7.0?p7.3 i/o i 4-bit i/o ports. 1-bit or 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. ports 6 and 7 can be paired to enable 8-bit data transfer. 31?34 (26?29) 35?38 (30?33) ks0?ks3 ks4?ks7 d-4 p8.0?p8.3 p9.0?p9.2 i/o i 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. ports 8 and 9 can be paired to enable 8-bit data transfer. 23?26 (18?21) 40?42 (35?37) ? d-2
product overview s3 c7524/c7528/p7528/c7534/c7538/p7538 1- 8 table 1-1. s3c7524/c7528 pin descriptions (continued) pin name pin type reset value description pin number share pin circuit type dtmf o ? dtmf output. 39 (34) ? g-6 btco i/o i basic timer clock output 16 (10) p4.0 e-2 int0 int1 i i external interrupts. the triggering edge for int0 and int1 is selectable. 1 (39) 2 (40) p1.0 p1.1 a-3 int2 i i quasi-interrupt with detection of rising edges 3 (41) p1.2 a-3 int4 i i external interrupt with detection of rising and falling edges. 4 (42) p1.3 a-3 tclo0 i/o i timer/counter 0 clock output 5 (43) p2.0 d-2 tclo1 i/o i timer/counter 1 clock output 6 (44) p2.1 d-2 clo i/o i clock output 7 (1) p2.2 d-2 buz i/o i 2 khz, 4 khz, 8 khz, or 16 khz frequency output at the watch timer clock frequency of 4.19 mhz for buzzer sound 8 (2) p2.3 d-2 tcl0 i/o i external clock input for timer/counter 0 9 (3) p3.0 d-4 tcl1 i/o i external clock input for timer/counter 1 10 (4) p3.1 d-4 ks0?ks3 ks4?ks7 i/o i quasi-interrupt inputs with falling edge detection 31?34 (26?29) 35?38 (30?33) p6.0? p6.3 p7.0? p7.3 d-4 v dd ? ? power supply 11 (5) ? ? v ss ? ? ground 12 (6) ? ? reset ? ? reset signal 18 (12) ? b x in x out ? ? crystal, or ceramic oscillator signal for main system clock. (for external clock input, use x in and input x in 's reverse phase to x out ) 14 (8) 13 (7) ? ? test ? ? test signal input 15 (9) ? ? nc ? ? no connection (16, 38) ? ? note: parentheses indicate pin number for 44 qfp package.
s3c7524/c7528/p7528/c7534/c7538/p7538 p roduct overview 1 - 9 table 1-2. s3c7534/c7538 pin descriptions pin name pin type description pin number share pin circuit type p1.0 i 1-bit input port. 1-bit and 4-bit read and test is possible. each bit pull-up resistors are assignable. 23 (25) int0 a-4 p2.0 p2.1 p2.2 p2.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. 24 (26) 25 (27) 26 (28) 27 (29) tclo0 tclo1 clo buz d-2 p3.0 p3.1 ports 2 and 3 can be paired to enable 8-bit data transfer. 28 (30) 29 (31) tcl0 tcl1 d-4 p4.0 p4.1 p4.2 p4.3 p5.0?p5.3 i/o 4-bit i/o ports. 1-bit and 4-bit read/write and test is possible. each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. the n-channel open-drain or push-pull output can be selected by software (1-bit unit). ports 4 and 5 can be paired to enable 8-bit data transfer. 5 (5) 6 (6) 8 (8) 9 (10) 10?13 (11?14) btco e-2 p6.0?p6.3 p7.0?p7.3 i/o 4-bit i/o ports. 1-bit and 4-bit read/write and test is possible. each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. ports 6 and 7 can be paired to enable 8-bit data transfer. 14?17 (15?18) 18?21 (19?22) ks0?ks3 ks4?ks7 d-4
product overview s3 c7524/c7528/p7528/c7534/c7538/p7538 1- 10 table 1-1. s3c7534/c7538 pin descriptions (continued) pin name i/o type description pin number share pin circuit type dtmf o dtmf output. 22 (23) ? g-6 int0 i external interrupt input. the triggering edge for int0 is selectable. 23 (25) p1.0 a-3 tclo0 i/o timer/counter 0 clock output 24 (26) p2.0 d-2 tclo1 i/o timer/counter 1 clock output 25 (27) p2.1 d-2 clo i/o clock output 26 (28) p2.2 d-2 buz i/o 2 khz, 4 khz, 8 khz, or 16 khz frequency output at the watch timer clock frequency of 4.19 mhz for buzzer sound 27 (29) p2.3 d-2 tcl0 i/o external clock input for timer/counter 0 28 (30) p3.0 d-4 tcl1 i/o external clock input for timer/counter 1 29 (31) p3.1 d-4 btco i/o basic timer clock output 5 (5) p4.0 e-2 v dd ? power supply 30 (32) ? ? v ss ? ground 1 (1) ? ? x in x out ? crystal, or ceramic oscillator signal for main system clock. (for external clock input, use x in and input x in 's reverse phase to x out ) 3 (3) 2 (2) ? ? nc ? no connection (9, 24) ? ? test ? test signal input 4 (4) ? ? reset ? reset signal 7 (7) ? b ks0?ks3 ks4?ks7 i/o quasi-interrupt inputs with falling edge detection 14?17 (15?18) 18?21 (19?22) p6.0? p6.3 p7.0? p7.3 d-4 note: parentheses indicate the pin number for 32-sop package.
s3c7524/c7528/p7528/c7534/c7538/p7538 p roduct overview 1 - 11 pin circuit diagrams v dd p - channel in n - channel figure 1?6. pin circuit type a schmitt trigger v dd pull-up resistor in figure 1?7. pin circuit type b p - channel resistor enable v dd pull-up resistor schmitt trigger in figure 1?8. pin circuit type a-4 data output disable out v dd p - channel n - channel figure 1?9. pin circuit type c
product overview ks 57c5204/c5208/p5208/c5304/c5308/p5308 microcontroller 1- 12 p-channel pull-up resistor resistor enable data output disable i/o v dd circuit type c figure 1?10. pin circuit type d-2 p-channel pull-up resistor resistor enable data output disable schmitt triger i/o v dd circuit type c figure 1?11. pin circuit type d-4 data output disable v dd p - channel pull-up resistor enable n - channel pne v dd pull-up resistor i/o figure 1?12. pin circuit type e-2 output disable dtmf out figure 1?13. pin circuit type g-6
s3c7524/c7528/p7528/c7534/c7538/p7538 el ectrical data 13? 1 13 electrical data in this section, information on s3c7524/c7528 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maximum ratings ? d.c. electrical characteristics ? system clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in and x out ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when i nitiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3c7 524/c7528/p7528/c7534/c7538/p7538 13? 2 table 13-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i1 all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 15 ma all i/o ports active ? 35 output current low i ol one i/o port active + 30 (peak value) ma + 15 (note) all i/o ports active + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low ( i ol ) are calculated as peak value duty . table 13-2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ? v ih3 0.7 v dd ? v dd v v ih2 ports 1, 3, 6, 7, and reset 0.8 v dd v dd v ih3 x in and x out v dd ? 0.1 v dd input low voltage v il1 all input pins except those specified below for v il2 ?v il3 ? ? 0.3 v dd v v il2 ports 1, 3, 6, 7, and reset 0.2 v dd v il3 x in and x out 0.1
s3c7524/c7528/p7528/c7534/c7538/p7538 el ectrical data 13? 3 table 13-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units output high voltage v oh i oh = ? 1 ma ports except 1 v dd ? 1.0 ? ? v output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 15 ma, ports 4 and 5 only ? 0.4 2 v v dd = 2.0 to 5.5 v, i ol = 1.6ma ? ? 0.4 v ol2 v dd = 4.5 v to 5.5 v i ol = 4 ma, all out ports except 4,5 ? ? 2 v v dd = 2.0 to 5.5 v, i ol = 1.6ma ? ? 0.4 input high leakage current i lih1 v i = v dd all input pins except those specified below ? ? 3 a i lih2 v i = v dd x in and x out 20 input low leakage current i lil1 v i = 0 v all input pins except below and reset ? ? ? 3 a i lil2 v i = 0 v x i n and x out only ? 20 output high leakage current i loh v o = v dd all out pins ? ? 3 a output low leakage current i lol v o = 0 v x in and x out only ? ? ? 3 a pull-up resistor r l1 v dd = 5 v; v i = 0 v except reset 25 47 100 k w v dd = 3 v 50 95 200 r l2 v dd = 5 v; v i = 0 v; reset 100 220 400 v dd = 3 v 200 450 800
electrical data s3c7 524/c7528/p7528/c7534/c7538/p7538 13? 4 table 13-2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (dtmf on) run mode; v dd = 5 v 10% (2) 3.58 mhz crystal oscillator, c1 = c2 = 22 pf ? 2.9 5.0 ma v dd = 3 v 10% 1.6 3.0 i dd2 run mode; v dd = 5 v 10% 6.0 mhz ? 2.6 8.0 ma (dtmf off) crystal oscillator, c1 = c2 = 22 pf 3.58 mhz 1.8 4.0 v dd = 3 v 10% 6.0 mhz 1.8 4.0 3.58 mhz 1.2 2.3 i dd 3 idle mode; = v dd = 5 v 10% 6.0 mhz ? 0.7 2.5 ma crystal oscillator, c1 = c2 = 22 pf 3.58 mhz 0.6 1.8 v dd = 3 v 10% 6.0 mhz 0.3 1.5 3.58 mhz 0.2 1.0 i dd4 stop mode; v dd = 5 v 10% ? 0.01 3 a stop mode; v dd = 3 v 10% 0.01 2 row tone level v row v dd = 5 v 10% v dd = 3 v 10% v dd = 2 v rl = 5k w ? 16.0 ? 14.0 ? 11.0 dbv ratio of column to row tone db cr v dd = 5 v 10% v dd = 3 v 10% v dd = 2 v rl = 5k w 1 2 3 distortion (dual tone) thd v dd = 5 v 10% v dd = 3 v 10% v dd = 2 v rl = 5k w , 1mhz band ? ? 5 % notes 1. d.c. electrical values f or supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up registers. 2. for d.c. electrical values , the power control register (pcon) must be set to 0011b.
s3c7524/c7528/p7528/c7534/c7538/p7538 el ectrical data 13? 5 table 13-3. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 2.0 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5v 0.4 ? 4.2 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3c7 524/c7528/p7528/c7534/c7538/p7538 13? 6 table 13-4. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 13-5. a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time (1) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s v dd = 2.0 v to 5.5 v 0.95 tcl0, tcl1 input frequency f ti0 , f ti1 v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 2.0 v to 5.5v 1 mhz tcl0, tcl1 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 2.0 v to 5.5 v 1.8 interrupt input high, low width t inth , t intl int0, int1, int2, int4, ks0?ks7 10 ? ? s reset input low width t rsl input 10 ? ? s
s3c7524/c7528/p7528/c7534/c7538/p7538 el ectrical data 13? 7 cpu clock = oscillator frequency x 1/n (n = 4, 8, 64) supply voltage (v) 1.05 m hz 1.5 mhz 15.625 khz cpu clock 1 2 3 4 5 6 7 6 mhz 4.2 mhz 2.7 v main osc. freq. figure 13-1. standard operating voltage range table 13-6. ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.5 ? 5.5 v data retention supply current i dddr v dddr = 1.5 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by reset released by interrupt ? 2 17 /fx (2) ? ms ms notes 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
electrical data s3c7 524/c7528/p7528/c7534/c7538/p7538 13? 8 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode figure 13-2. stop mode release timing when initiated by reset reset v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal operating mode power-down mode terminating signal (interrupt request) figure 13-3. stop mode release timing when initiated by interrupt request
s3c7524/c7528/p7528/c7534/c7538/p7538 el ectrical data 13? 9 timing waveforms (continued) 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 13-4. a.c. timing measurement points (except for x in ) x in t xl t xh 1 / f x v dd - 0.1 v 0.1 v figure 13-5. clock timing measurement at x in tcl t til t tih 1 / f ti 0.8 v dd 0.2 v dd figure 13-6. tcl timing
electrical data s3c7 524/c7528/p7528/c7534/c7538/p7538 13? 10 t rsl reset 0.2 v dd figure 13-7. input timing for reset reset signal int0, 1, 2, 4 k0 to k7 t intl t inth 0.8 v dd 0.2 v dd figure 13-8. input timing for external interrupts and quasi-interrupts
s3c7524/c7528/p7528/c7534/c7538/p7538 mechanical data 1 4 ? 1 1 4 mechanical data this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram ? pad/pin coordinate data table note : dimensions are in millimeters. 39.50 max 39.10 0 .20 0.50 0.10 1.78 (1.77) 0.51 min 3.30 0.30 3.50 0.20 5.08 max 42-sdip-600 0-15 1.00 0.10 0.25 + 0.10 - 0.05 15.24 14.00 0 .20 #42 #22 #21 #1 figure 14- 1. 42 -sdip- 6 00 package dimensions
mechanical data s3c7524/c7528/p7528/c7534/c7538/p7538 14 ? 2 44-qfp-1010b #44 note : dimensions are in millimeters. 10.00 0.20 13.20 0.30 10.00 0.20 13.20 0.30 #1 0.35 + 0.10 - 0.05 0.80 0.10 max 0.80 0.20 0.05 min 2.05 0.10 2.30 max 0.15 + 0.10 - 0.05 0-8 0.15 max (1.00) figure 14-2 . 44 - qfp - 1010b package dimensions
s3c7524/c7528/p7528/c7534/c7538/p7538 mechanical data 1 4 ? 3 note : dimensions are in millimeters. 27.88 max 27.48 0 .20 (1.30) 30-sdip-400 8.94 0 .20 #30 #1 0.56 0.10 1.12 0.10 3.81 0.20 5.21 max 1.778 0.51 min 3.30 0.30 #16 #15 0-15 0.25 + 0.10 - 0.05 10.16 figure 14-3 . 30 - sdip - 400 package dimensions
mechanical data s3c7524/c7528/p7528/c7534/c7538/p7538 14 ? 4 32-sop-450a 20.30 max 19.90 0 .20 #17 #16 0-8 0.25 + 0.10 - 0.05 11.43 8.34 0.20 0.90 0.20 0.05 min 2.00 0.10 2.20 max 0.10 max 1.27 note : dimensions are in millimeters. 12.00 0 .30 #32 #1 (0.43) 0.40 0.10 figure 14-4 . 32-sop-450a package dimensions
s3c7524/c7528/p7528/c7534/c7538/p7538 s3 p7528/p7538 otp 1 5? 1 1 5 s3p7528/p7538 otp overview the s3p7528/p7538 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c7524/c7528/c7534/c7538 microcontroller. it has an on-chip eprom instead of masked rom. the eprom is accessed by a serial data format. the s3p7528/p7538 is fully compatible with the s3c7528/c7538, both in function and in pin configuration. because of its simple programming requirements, the s3p7528/p7538 is ideal for use as an evaluation chip for the s3c7528/c7538. p1.0 / int0 p1.1 / int1 p1.2 / int2 p1.3 / int4 p2.0 / tclo0 p2.1 / tclo1 p2.2 / clo p2.3 / buz sdat / p3.0 / tcl0 sclk / p3.1 / tcl1 v dd / v dd v ss / v ss x out x in v pp / test p4.0 / btco p4.1 reset reset / reset p3.2 p3.3 p4.2 p9.2 p9.1 p9.0 dtmf p7.3 / ks7 p7.2 / ks6 p7.1 / ks5 p7.0 / ks4 p6.3 / ks3 p6.2 / ks2 p6.1 / ks1 p6.0 / ks0 p5.3 p5.2 p5.1 p5.0 p8.3 p8.2 p8.1 p8.0 p4.3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 note: the bold words indicate otp pin names. s3p7528 (42-sdip-600) figure 15-1. s3p7528 pin assignments (42-sdip)
s3p7528/p7538 otp s3c7524/c7528/p7528/c7534/c7538/p7538 15? 2 v ss / v ss x out x in v pp / test p4.0 / btco p4.1 reset reset / reset p4.2 nc p4.3 p5.0 p5.1 p5.2 p5.3 p6.0 / ks0 p6.1 / ks1 v dd / v dd p3.1 / tcl1 / sclk p3.0 / tcl0 / sdat p2.3 / buz p2.2 / clo p2.1 / tclo1 p2.0 / tclo0 p1.0 / int0 nc dtmf p7.3 / ks7 p7.2 / ks6 p7.1 / ks5 p7.0 / ks4 p6.3 / ks3 p6.2 / ks2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (32-sop-405a) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ks57p5308 figure 15-2. s3p7528 pin assignments (44-qfp)
s3c7524/c7528/p7528/c7534/c7538/p7538 s3 p7528/p7538 otp 1 5? 3 v ss / v ss x out x in v pp / test p4.0 / btco p4.1 reset reset / reset p4.2 p4.3 p5.0 p5.1 p5.2 p5.3 p6.0 / ks0 p6.1 / ks1 v dd / v dd p3.1 / tcl1 / sclk p3.0 / tcl0 / sdat p2.3 / buz p2.2 / clo p2.1 / tclo1 p2.0 / tclo0 p1.0 / int0 dtmf p7.3 / ks7 p7.2 / ks6 p7.1 / ks5 p7.0 / ks4 p6.3 / ks3 p6.2 / ks2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 (30-sdip-400) S3C7538 figure 15-3. s3p7538 pin assignments (30-sdip)
s3p7528/p7538 otp s3c7524/c7528/p7528/c7534/c7538/p7538 15? 4 v ss / v ss x out x in v pp / test p4.0 / btco p4.1 reset reset / reset p4.2 nc p4.3 p5.0 p5.1 p5.2 p5.3 p6.0 / ks0 p6.1 / ks1 v dd / v dd p3.1 / tcl1 / sclk p3.0 / tcl0 / sdat p2.3 / buz p2.2 / clo p2.1 / tclo1 p2.0 / tclo0 p1.0 / int0 nc dtmf p7.3 / ks7 p7.2 / ks6 p7.1 / ks5 p7.0 / ks4 p6.3 / ks3 p6.2 / ks2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (32-sop-405a) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 s3p7538 figure 15-4. s3p7538 pin assignments (32-sop)
s3c7524/c7528/p7528/c7534/c7538/p7538 s3 p7528/p7538 otp 1 5? 5 table 15-1. s3p7528 pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.0 sdat 9 (3) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p3.1 sclk 10 (4) i/o serial clock pin. input only pin. test v pp (test) 15 (9) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 18 (12) i chip initialization v dd / v ss v dd / v ss 11/12 (5/6) i logic power supply pin. v dd should be tied to +5 v during programming. note: parentheses indicate pin numbers of 44 qfp package. table 15-2. s3p7538 pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.0 sdat 28 (30) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p3.1 sclk 29 (31) i/o serial clock pin. input only pin. test v pp (test) 4 (4) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 7 (7) i chip initialization v dd / v ss v dd / v ss 30/1 (32/1) i logic power supply pin. v dd should be tied to +5 v during programming. note: parentheses indicate pin numbers of 32 sdip package.
s3p7528/p7538 otp s3c7524/c7528/p7528/c7534/c7538/p7538 15? 6 table 15-3. comparison of s3p7528 and s3c7528 features characteristic s3p7528 s3c7528 program memory 8 k byte eprom 8 k byte mask rom operating voltage (v dd ) 2.0 v to 5.5 v 2.0 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 42 sdip / 44 qfp 42 sdip / 44 qfp eprom programmability user program 1 time programmed at the factory table 15-4. comparison of s3p7538 and S3C7538 features characteristic s3p7538 S3C7538 program memory 8 k byte eprom 8 k byte mask rom operating voltage (v dd ) 2.0 v to 5.5 v 2.0 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 30 sop / 32 sop 30 sop / 32 sop eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p7528, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 15-3 below. table 15-5. operating mode selection criteria v dd vpp (test) reg/ mem mem address (a15-a0) r/ w w mode 5 v 5 v 0 0000h 1 eprom read 12.5v 0 0000h 0 eprom program 12.5v 0 0000h 1 eprom verify 12.5v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
s3c7524/c7528/p7528/c7534/c7538/p7538 s3 p7528/p7538 otp 1 5? 7 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 15-5. otp programming algorithm
s3p7528/p7538 otp s3c7524/c7528/p7528/c7534/c7538/p7538 15? 8 notes

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